OpenAI and Broadcom Unveil Jalapeño Custom AI Inference Chip

OpenAI and Broadcom have unveiled Jalapeño, OpenAI’s first custom AI accelerator chip designed specifically for large language model inference.

By Olivia Grant Published: Updated:

OpenAI and Broadcom have unveiled Jalapeño, OpenAI’s first custom AI accelerator chip, designed from the ground up for large language model inference. The announcement was made jointly by OpenAI President Greg Brockman and Broadcom CEO Hock Tan, with engineering samples already running ML workloads in the lab at production target frequency and power, including GPT-5.3-Codex-Spark.

Unlike general-purpose accelerators adapted from earlier AI workloads, Jalapeño was architected specifically around OpenAI’s understanding of LLM inference requirements, drawing on workloads running across ChatGPT, Codex, and its developer API.

The chip’s architecture reduces data movement and balances compute, memory, and networking resources to achieve utilization closer to theoretical peak performance. Early testing indicates the chip will deliver substantially better performance per watt than current state-of-the-art accelerators, though a detailed technical report is expected in the coming months.

The full development cycle from initial design to manufacturing tape-out took nine months, which OpenAI described as the fastest ASIC development cycle ever achieved in high-performance advanced semiconductors. OpenAI models were used to accelerate parts of the design and optimization process.

Broadcom contributed silicon implementation and networking technologies, including its Tomahawk networking silicon. Celestica is supporting board, rack, and system integration. The three companies are building what they describe as a multi-generation compute platform, with initial deployment targeted for the end of 2026 and expansion planned in subsequent years.

Hock Tan said the partnership is designed to enable gigawatt-scale data center deployments with Microsoft and other partners starting in 2026. OpenAI framed the chip as a core element of its full-stack infrastructure strategy, spanning chip architecture, memory systems, networking, scheduling, and deployment infrastructure.

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